For MDPP-16 the following software is available: CSI = Processing of charge integrated signals calculates short shaped amplitudes and long shaped amplitudes and Timing. Typical signals from CsI scintillator light with PMT and Charge preamp, Signal from 3He tubes for n-detection. Pulse shape discrimination of Si-Detector signals. Outputs: short integrated Amplitude 64k, long integrated Amplitude 64k, Timing 64k channels with min 24ps SCP = Signal Processing of Standard Charge Integrating Preamplifiers Outputs: Amplitude 64k, Timing 64k channels with min 24ps RCP = Signal Processing of Reset Charge Integrating Preamplifiers Outputs, typically germanium detectors: Amplitude 64k, Timing 64k channels with min 24ps QDC = Signal Processing of fast PMT signals, Pulse Shape Discrimination, timing Outputs: Amplitude Short 64k, Amplitude Long 64k, Timing 64k channels with min 24ps PADC = Peak sensing ADC with Baseline Restorer, self triggering. The peak maximum is used to determine a high quality timing. Amplitude Long 64k, Timing 64k channels with min 24ps Revisions for Hardware 1.x: CSI = V5002. 7xIrq-trigger, FMBLT waitstate: 0x6006 = 0 SCP = V2021: updated BLR 7xIrq-trigger, FMBLT waitstate: 0x6006 = 0 SCP = V2022: BLR range extended for noisy signals to +-12% full range RCP = V1020: updated BLR 7xIrq-trigger, FMBLT waitstate: 0x6006 = 0 QDC = V3020 7xIrq-trigger, FMBLT waitstate: 0x6006 = 0 Extended short (128) / long(512) integration 0x6046 sets resolution 65k...4k (set val 0...4) Changed to PT concept: short and TF in same path, zero crossing instead of CFD. V3021 -> fixed BLR jumps at some specific signals PADC = V4001: 7xIrq-trigger, FMBLT waitstate: 0x6006 = 0 Revisions for Hardware 1.x and new VME64X: 2.x VME64X module is compatible to VME64. CSI = V5030. Revised VME inerface timing (Dread, BLT, MBLT) VME64X slot address when coders are set to 0xFFFF Fixed bug for simultaneouis external triggers and multi hit = 0. SCP = V2030: Revised VME inerface timing (Dread, BLT, MBLT) VME64X slot address when coders are set to 0xFFFF Fixed bug for simultaneouis external triggers and multi hit = 0. RCP = V1030: Revised VME inerface timing (Dread, BLT, MBLT) VME64X slot address when coders are set to 0xFFFF Fixed bug for simultaneouis external triggers and multi hit = 0. QDC = V3030 Revised VME inerface timing (Dread, BLT, MBLT) VME64X slot address when coders are set to 0xFFFF Fixed bug for simultaneouis external triggers and multi hit = 0. PADC = V4030: Revised VME inerface timing (Dread, BLT, MBLT) VME64X slot address when coders are set to 0xFFFF Fixed bug for simultaneouis external triggers and multi hit = 0. SCP = V2031: Bug in widow of interest with external trigger fixed CSI = V5031: Bug in widow of interest with external trigger fixed package 0031 for MDPP-16 contains the following software: Area 0: CSI = V5031. Area 1: SCP = V2031: Area 2: RCP = V1030: Area 3: QDC = V3030 Not in Package: PADC = V4030 *** SP0033 All softwares modified for new MDPP-16 hardware (downward compatible) Previous software with new hardware loads DS1 line. -> modules of other manufacturer may not respond to read and write on Bus. *** SP0034 QDC software -> 3032: mon flicker mark fixed, bug in individual setting of short integration fixed. Singel event release bug fixed. *** SP0035 SCP software -> 2034 allow store of calibration for new Flash Adesto AT25SF128 QDC software -> 3033: reconstrained timing to solve header loss errors in some crates. *** SP0036 all softwares: new VME interface 10.10.2022, 2ESST implemented, CBLT problems solved, no 6034 after Daq start 603A required. Improved internal timing. Data counter 0x6030 bug at MBLT transfer fixed. Improved power up timing. Area 0: CSI = V5033. Area 1: SCP = V2035: Area 2: RCP = V1034: Area 3: QDC = V3033 *** SP0039 Fixed bug when window of interest is created from external trigger, and has to be delayed. 2ESST address bug fixed. Area 0: CSI = V5037. Area 1: SCP = V2039: Area 2: RCP = V1038: Area 3: QDC = V3037 Not in Packet: PADC = V4036; choose Area at programming *** SP0040 2ESST retry bug fixed. Runs at speed=1 =160MBytes/s -MDPP-boards starting wit V22 provide "Retry", DS1. Boards before always send even number of 64bit words. Unused words are 2x 0xFFFFFFFF, DS1: data transfer starts after some 100ns delay. -lower 5 LEDS blinking red/yellow when Sysclock fails. -SCP,RCP,QDC improved timing by correction tables. Area 0: CSI = V5038. Area 1: SCP = V2040: Area 2: RCP = V1039: Area 3: QDC = V3038 Not in Packet: PADC = V4037; choose Area at programming *** SP0041 -Revised power up procedure Area 0: CSI = V5038. Area 1: SCP = V2041: # Streaming mode implemented Area 2: RCP = V1039: Area 3: QDC = V3038 Not in Packet: PADC = V4037; choose Area at programming *** SP0041 -All modules: A24 addressing requires two high coders to be 0x00 Area 0: CSI = V5039. Area 1: SCP = V2043: Added adjustable BLR offset, Deconv optimised. Area 2: RCP = V1041: Area 3: QDC = V3039 Not in Packet: PADC = V4038; Added adjustable BLR offset, Deconv optimised. choose Area at programming *** SP0042 -All modules: A24 addressing requires two high coders to be 0x00 Area 0: CSI = V5039. Area 1: SCP = V2043: Added adjustable BLR offset, Deconv optimised. Area2: RCP = V1041 Area 3: QDC = V3039 Not in Packet: :PADC = V4038; Added adjustable BLR offset, Deconv optimised. choose Area at programming Not in Packet: :PADC = V4039; Fixed external trigger issue, did not work. choose Area at programming *** SP0043 -All firmwares: 2ESST event number release did not work correctly beyond 512 words -> fixed -All firmwares: counter bank latching at low register read corrected -in sampling mode and WOI mode, bit26 is set in header to mark 16 bit extended event length Area0: CSI = V5040 Area 1: SCP = V2050, 2 streaming modes,,streaming synchronised to sysclk, sample output implemented Area2: RCP = V1042 Area 3: QDC = V3050, 2 streaming modes,streaming synchronised to sysclk, sample output implemented Not in Packet: :PADC = V4041; Fixed external trigger issue, did not work. choose Area at programming *** SP0044 -in streaming mode and WOI mode, bit24 is set in header to mark sampling mode with 16 bit extended event length Area0: CSI = V5040 Area 1: SCP = V2052, prediff adapted with sample trail length, Stability at very long shaping time improved, Header for standard streaming corrected Area2: RCP = V1042 Area 3: QDC = V3050, Header for standard streaming corrected, Long integration limit 3.2us -> 6.4us, roll over bug fixed. Adapt prediff time to sample trail length Not in Packet: :PADC = V4041; choose Area at programming *** MDPP16_CSI_SCP_RCP_QDC_SP0044.mvp (Thu Aug 7 09:56:54 AM CEST 2025) - Repack to fix the filename of the QDC firmware.