For MDPP-32 the following software is available:


SCP = Signal Processing of Standard Charge Integrating Preamplifiers
	Outputs: 
	 	Amplitude 64k, 
		Timing 64k channels with min 24ps

QDC = Signal Processing of fast PMT signals, Pulse Shape Discrimination, timing 
	Outputs: Amplitude Short 64k, 
		 Amplitude Long 64k,
		  Timing 64k channels with min 24ps

PADC = Peak sensing and timing for shaped pulses. Self triggered 
	or external, up to 32k resolution.
	 Timing 64k channels with min 24ps


******************************************************************************************
** Packets and Updates ************************************************************************
******************************************************************************************
SP0025
Area 0: SCP = V2050  //  Sampling implemented. Can send sample trails with up to 500 samples per channel
Area 1: QDC = V3050 	//  as in SP24, send sample trails up to 1000 samples per channel. Also overlapping trails possible.
Area 2: PADC = V4021  // 

SP0024
Area 0: SCP = V2024  // Streming modes implemented. Sysclk synchronisation at streaming mode 
Area 1: QDC = V3050 	// Streaming modes implemented,  Sysclk synchronisation at streaming mode, Sampling mode
Area 2: PADC = V4021  // fix event counter latching  
For all softwares: external synchronisation input fixed

SP0022
Area 0: SCP = V2021 
Area 1: QDC = V3017 
Area 2: PADC = V4019  
Fix for SCP, PADC software: self trigger bug fixed. Both banks triggering results in only bank0 triggering
For all softwares: when time difference runs out, max value and overflow bit is emitted. Before: time stamp was not emitted.

SP0021
Area 0: SCP = V2020 	# Limit for shaping time corrected: 8 to 1000 (100ns to 12.5us) ,  input decon improved
Area 1: QDC = V3017 
Area 2: PADC = V4018  # blr_threshold implemented, input decon improved

SP0020
Area 0: SCP = V2018 	 
Area 1: QDC = V3017 
Area 2: PADC = V4015 
common changes: VME A24 addressing: module only responds when high byte coders == 0x00
	Trigger output fixed: Bank0/1 triggers and individual channel triggers can be register selected

SP0019
Area 0: SCP = V2017 	# Streaming mode implemented  
Area 1: QDC = V3016 
Area 2: PADC = V4015
common changes: ESST fix: number of released events could differ from specified. Revised power up procedure.

SP0018
Area 0: SCP = V2016   
Area 1: QDC = V3015 
Area 2: PADC = V4014
ESST fix, retry line bug, 
Blink signal on lower 5 LEDs when VME-Sysclock fails.
SCP: correction table for timing -> 50..60ps rms also at long int.

SP0017
Area 0: SCP = V2015   
Area 1: QDC = V3014 
Area 2: PADC = V4013
Improved channel synchronisation of ADC links
Fixed bug when external trigger comes early and has to be delayed for win of interest.
Fixed addressing bug in 2ESST.

SP0014
2ESST implemented 160 and 320 MB/s
Area 0: SCP = V2012   
Area 1: QDC = V3012 
Area 2: PADC = V4010 

SP0013b
All software: DS1 driver bug fixed.
Area 0: SCP = V2010:   
Area 1: QDC = V3010 
Area 2: PADC = V4009 

package 0012 for MDPP-32 contains the following software:
Area 0: SCP = V2009:   
Area 1: QDC = V3009 
Area 2: PADC = V4007