MVLC_100... is intended for MVLC with large FPGA (standard)
MVLC_45...  for small FPGA. For very few devices of first series

MVLC_45 no longer supported, not enough resources for new features

MVLC_100/45_FW0012 trigger_io updates (daq_start)

FW0015 event stamper with output buffer implemented.
	6010 irq_level0[2:0]  // For threshold 0;  1 to 7; 0 = off
	6012 irq_level1[2:0] 	 // For Threshold 1;  Internal IRQ, 
	603A start_events 	 // accumulate time stamps
	601E irq_event_threshold0[15:0] // max 4k events 
	6018 irq_event_threshold1[15:0] // max 4k events
	6016 max_transfer_data[15:0] // number of time stamps transfered in one BLT access

FW0017 DSO built in 
	fixed strobed LUT bugs: 
	8x universal utils: when used as IRQ inputs

FW0018 DSO built in, scans NIM inputs, 6x IRQ inputs 
	  Collision bug Counter read and Counter0-FIFO read fixed.

FW0020 VME bus timeout increased from 1.6us to 16us
	Multi crate synchronisation implemented in Hardware
	Some new stack commands implemented (still undocumented)
FW0021 Multicrate features implemented, CR/CSR space addressing for 	some modules (am codes extended). Timing optimisations
FW0022 Multicrate synchronisation improved; 
	 Error capture at VME read/write -> blink signal at front LEDs
FW0023 extend signal to IRQ translation table to 8 entries (0x7000 to 	0x701E)
FW0024 new Reg 0x7020 : assign unassigned signals to specified 	internal IRQ
	Fix Trig IO glitches (from FW0022)
FW0026 minor fixes, 
	max Stack size increased from 1kWords to 2kWords.
	read/write with Berr response -> fixed error message.